1. Field of the Invention
The present invention relates to a system and method for controlling data transmission between different data buses, and more particularly, to a system and method for controlling data realignment using byte selection data representing different byte locations.
2. Description of the Related Art
In general, an interbus data flow control system serves to realign data between different buses and is directed to byte-swapping.
FIG. 1 illustrates an SGC data bus and an i486 data bus. The SGC data bus is of a byte-wise big-endian type and the i486 data bus is of a byte-wise little-endian type. Big-endians and little-endians are divisions according to byte ordering in data buses. That is, a little-endian is provided with a byte ordering structure having a reverse sequential order of "0, 1, 2, 3" starting at the LSB (Least Significant Bit), and a big-endian is provided with a byte ordering structure having a sequential order of "0, 1, 2, 3" staring at the MSB (Most Significant Bit).
As illustrated in FIG. 2, a conventional interbus data flow control apparatus includes a swapping control unit 10 for controlling data flow in a buffer, and a data swapping unit 20 for determining a data flow direction and for transmitting data output from different data buses.
The swapping control unit 10 includes an alignment type determining register 11 for determining whether the alignment of a data transmission bus system for transmitting data is identical to the alignment of a data reception bus system for receiving the data, and a control signal generator 12 for decoding an address signal corresponding to the data transmission bus system in accordance with the determination of the alignment type determining register 11.
The data swapping unit 20 is provided with a first bidirectional buffer 21 adjacent to the SGC data bus and a second bidirectional buffer 22 adjacent to the i486 data bus for determining a data flow direction and transferring data between different buses. A unidirectional buffer 23 in the data swapping unit 20 outputs a control signal to each of the first and second buffers 21 and 22 to output data in accordance with the data flow direction determined in the first or second bidirectional buffer 21 or 22.
With reference to FIGS. 1 and 2, the operation of the above-described conventional data flow control system will now be described in further detail where data is transferred from the SGC data bus to the i486 data bus.
In this example, when a data is transmitted from the SGC data bus to the first bidirectional buffer 21, the alignment type determining register 11 in the swapping control unit 10 determines whether the data bus system for transmitting data is aligned with the i486 data bus system for receiving the data. The alignment type determining register 11 denotes a register with a reference address signal preset thereto in order to determine whether the alignment of the data bus system for transmitting data is identical to that of the data bus system for receiving the transferred data.
In accordance with the determination of the alignment type determining register 11, the control signal generator 12 decodes an address signal for swapping the data and outputs a control signal to control the data swapping unit 20.
The unidirectional buffer 23 in the data swapping unit 20 then outputs a control signal to the first bidirectional buffer 21 in accordance with the control signal output from the control signal generator 12. The first bidirectional buffer 21 receives the control signal from the unidirectional buffer 23 and outputs the data from the SGC data bus to the second bidirectional buffer 22. The second bidirectional buffer 22 outputs the received data to the i486 data bus.
At this time, the 0th byte data (0 to 7 bits) from the SGC data bus are transferred to the third byte location in the i486 data bus through the first and second bi-directional buffers 21 and 22. Similarly, the first byte data (8 to 15 bits) in the SGC data bus are transferred to the second byte location of the i486 data bus, the second byte data (16 to 23 bits) in the SGC data bus are transferred to the first byte location of the i486 data bus, and the third byte data (24 to 31 bits) in the SGC data bus are transferred to the 0th byte location of the i486 data bus. Accordingly, all the data are transferred from the SGC data bus to the i486 data bus and the data are swapped in a reverse order.
However, the conventional interbus data flow control system increases a bus width depending on the data size for transmission and unnecessary data may be disadvantageously transmitted, thereby deteriorating applicability and expandability of data transmission.